Tcl Commands¶
This page describes the list of commands available in OpenLane, their functionality, and their expected inputs and outputs.
NOTE: You must run the prep
command before running any of the other commands, in order to have the necessary files and configurations loaded.
The following commands are available in the interactive mode: ./flow.tcl -interactive
, or in Tclsh using % package require openlane 0.9
.
General Commands¶
Most of the following commands’ implementation exists in this file
Command |
Flags |
Description |
---|---|---|
|
Sets the current netlist used by the flow to |
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Runs logic verification for the new netlist against the previous netlist, if |
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Sets the current def file used by the flow to |
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prepares the used lef files by the flow. This process includes merging the techlef and cells lef, generating a merged.lef. |
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prepares a liberty file (i.e. |
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The lib file to output the trimmed liberty into. Required. |
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The input liberty file to trim the cells from. Required. |
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If provided, it will only use |
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generates an exclude list file for a liberty file (i.e. |
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The lib file that the list will be trimmed from. This will general a |
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If provided, it will only use |
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If provided, it will create an environment variable with the file content. The variable will be named |
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Prepares a run in openlane or loads a previously stopped run in order to proceed with it. It calls |
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Specifies the design folder. A design folder should contain a |
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Allows you to override certain configuration environment variables for this run. Format: |
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Expose the following environment variables to |
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Flag to overwirte an existing run with the same tag. |
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Specifies a |
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Specifies a |
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Creates a tcl configuration file for a design. |
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Sets the verilog source code file(s) in case of using |
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Specifies the design’s configuration file for running the flow. |
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Sets a verbose output level. 0 disables verbose information and tool outputs. 1 enables verbose information but disables tool outputs. 2 and greater outputs everything. More verbose levels may be added over time, so if you want absolutely all output, set it to something like 99. |
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Removed: Default Behavior Disables outputing to the terminal. |
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Generates the padframe for a design based on the files and configurations under |
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specifies the |
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Saves the views of a given |
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Changes the save path for the lef files to |
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Changes the save path for the mag files to |
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Changes the save path for the def files to |
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Changes the save path for the gds files to |
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Changes the save path for the verilog files to |
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Changes the save path for the spice files to |
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Changes the save path for the save path for all the types of files to |
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Removed: Specifies the |
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Labels the pins of a given macro def according to the netlist for lvs. |
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LEF file needed to have a proper view of the netlist AND the input DEF. |
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DEF view of the design that has the connectivity information. |
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Name of the pin of the pad as it appears in the netlist def. |
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Output labeled def file. |
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Gives extra control on the rest of the flags of the labeling script. For more information on the other args that the script supports, run: |
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Generates a verilog netlist from a given def file. Stores the resulting netlist in |
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The def file to write a verilog netlist from. |
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A file to which the output of OpenROAD is logged. |
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Add power and ground pins, and save to |
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Creates obstructions in def and lef files. |
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DEF view of the design to write the obstruction into. |
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LEF file of the design to write the obstruction into. |
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Name of obstruction. |
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X coordinate to place the obstruction. |
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Y coordinate to place the obstruction. |
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The width of the obstruction. |
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The height of the macro obstruction. |
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if |
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the list of layer names on which to place the obstruction. |
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Extracts the core dimensions based on the existing set environment variables. The results are set into |
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The path to write the logs into. |
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Runs SPEF extraction on the |
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Runs antenna checks based on the value of |
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Runs antenna checks using OpenROAD’s Antenna Rule Checker on the |
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Saves environment variables to |
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Runs OpenSTA timing analysis on the current design, and produces a log under |
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Removed: sets the tracks on a layer to specific value. |
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DEF view of the design in which to edit the tracks values. |
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layer to change. |
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tmp file to read the new track values from. |
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tmp file to store the original value. |
Checker Commands¶
Most of the following commands’ implementation exists in this file
Command |
Flags |
Description |
---|---|---|
|
Checks if any cells were unmapped or any latches were produced in the generated netlist by yosys. |
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Checks if the netlist generated by yosys contains any assign statements. |
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Checks if the LEF was properly read in the floorplan stage. This is to detect if EXTRA_LEFS isn’t set correctly. |
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Checks if the LEF contains all pins, and that EXTRA_LEFS was set correctly. |
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Checks if clock tree synthesis was successful and clock nets were added. |
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Catches replace divergence and exits the flow because global placement failed. |
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Checks if macro placement was successful using basic placement. |
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Checks for DRC violations after routing and exits the flow if any was found. Controlled by |
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Checks for DRC violations after magic DRC is executed and exits the flow if any was found. Controlled by |
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Checks for LVS errors after netgen LVS is executed and exits the flow if any was found. Controlled by |
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The parsed LVS log, generated at the end of running LVS. The reason why this is passed over is because there are two types of LVS and each produces a different report, and this might be expanded later. |
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Checks for illegal overlaps during magic extraction. In some cases, these imply existing undetected shorts in the design. It also exits the flow if any was found. Controlled by |
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The magic extraction feedback log, generated at the end of running Magic extractions. |
Synthesis/Verilog Commands¶
Most of the following commands’ implementation exists in this file
Command |
Flags |
Description |
---|---|---|
|
Runs yosys synthesis on the design processed in the flow (the design is set by the |
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Sets the outputfile from yosys synthesis. |
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Runs yosys synthesis on the current design as well as OpenSTA timing analysis on the generated netlist. The logs are produced under |
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Runs synthesis exploration, which will try out the available synthesis strategies against the input design. The output will be the four possible gate level netlists under |
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Runs on structural verilog (top-level netlists) and elaborates it. The |
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Runs yosys to rewrite the verilog given in |
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Runs logic verification using yosys between the two given netlists. |
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The first netlist (lefthand-side) in the logic verification comparison. |
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The second netlist (righthand-side) in the logic verification comparison. |
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Removed: Read $::env(SYNTH_BIN) Returns the used binary for yosys. |
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Removed: Use |
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The input verilog that doesn’t contain the power pins and connections. |
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The output verilog file. |
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The LEF view with the power pins information. |
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The name of the power pin. |
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The name of the ground pin. |
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writes a verilog file that contains the power pins and connections from a DEF file. It stores the result in |
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The input ODB file. |
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The output DEF file. Required. |
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The output verilog file. Required. |
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The LEF view with the power pins information. |
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The name of the power pin. |
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The name of the ground pin. |
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The verilog netlist parsed from yosys that contains the internal power connections in case the design has internal macros file. |
Floorplan Commands¶
Most of the following commands’ implementation exists in this file
Command |
Flags |
Description |
---|---|---|
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Runs floorplanning on the processed design using the openroad app. The resulting file is under |
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Runs io placement on the design processed using the openroad app. The resulting file is under |
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Runs IO placement based on an input configuration file to place the pins in the orientation and order requiered by the user. |
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LEF file to be used. It must also include the technology information. |
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DEF file to be used. |
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configuration file containing the list of desired pin order. An example could be found here. The file should contain |
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The metal layer on which to place the io pins horizontally (top and bottom of the die). |
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The metal layer on which to place the io pins vertically (left and right of the die). |
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A multiplier for vertical pin thickness. Base thickness is the pins layer minwidth. |
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A multiplier for horizontal pin thickness. Base thickness is the pins layer minwidth. |
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Extends the vertical io pins outside of the die by the specified units. |
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Extends the horizontal io pins outside of the die by the specified units. |
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IO length to be used. |
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output DEF file to be written. |
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contextualizes io placement on a given macro (the processed design) with the context of the higher macro that contains it. This allows the io pins to be placed in location closer to what they will be connected with on the bigger macro. The resuls are saved under |
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LEF file needed to have a proper view of the top-level DEF |
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DEF view of the top-level design where the macro is instantiated. |
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Runs tap/decap placement on the design processed using the openroad app. The resulting file is under |
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Runs floorplanning on a chip removing pins section and other empty sections from the def. The resulting file is under |
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Runs |
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Applies the DIE_AREA, pin names, and pin locations excluding power and ground pins from |
Placement Commands¶
Most of the following commands’ implementation exists in this file
Command |
Flags |
Description |
---|---|---|
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Runs global placement on the processed design using OpenROAD. The resulting file is under |
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Alias for |
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Runs random global placement using a custom OpenROAD-based script. Useful for tiny designs. The resulting file is under |
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Runs detailed placement on the processed design using OpenROAD. The resulting file is under |
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Alias for |
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Writes a configuration file to be processed by |
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Uses the configuration file generated by |
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Runs basic macro placement on the chip level using the openroad app, and it writes into |
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Runs resizer design optimizations to insert buffers on nets to repair max slew, max capacitance, max fanout violations, and on long wires to reduce RC delay in the wire. It also resizes cells. |
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Runs global placement ( |
CTS Commands¶
Most of the following commands’ implementation exists in this file
Command |
Flags |
Description |
---|---|---|
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Runs clock tree synthesis using the openroad app on the processed design. The resulting file is under |
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Runs resizer timing optimizations which repairs setup and hold violations. |
Fill Insertion/Diode Insertion Commands¶
Most of the following commands’ implementation exists in this file
Command |
Flags |
Description |
---|---|---|
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Runs fill insertion on the processed design using the openroad app. The resulting file is under |
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Deprecated |
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Runs diode insertion on the processed design using an opendb custom script following diode insertion strategies 4 and 5. The resulting file is under |
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Deprecated |
PDN Generation Commands¶
Most of the following commands’ implementation exists in this file
Command |
Flags |
Description |
---|---|---|
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Runs basic power grid generation on the processed design using the openroad app. The resulting file is under |
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Performs power routing on a chip level design. More details in Chip Integration. |
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The input ODB file. |
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The name of the power pin. |
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The name of the ground pin. |
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The output DEF file path. |
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The output ODB file path. |
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Runs power grid generation with the advanced control options, |
Routing Commands¶
Most of the following commands’ implementation exists in this file
Command |
Flags |
Description |
---|---|---|
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Runs global routing on the processed design The resulting file is under |
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Runs global routing on the processed design using the openroad app’s fastroute. The resulting file is under |
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Runs detailed routing on the processed design. The resulting file is under |
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Runs detailed routing on the processed design using OpenROAD TritonRoute. The resulting file is under |
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Uses |
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Uses |
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Runs diode insertion based on the strategy, then adds the routing obstructions, followed by |
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Removed: Aliases global_routing_fastroute: Runs global routing on the processed design using cugr. The resulting file is under |
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Removed: Aliases detailed_routing_tritonroute: Runs detailed routing on the processed design using DRCU. The resulting file is under |
Magic Commands¶
Most of the following commands’ implementation exists in this file
Command |
Flags |
Description |
---|---|---|
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Streams the final GDS and a mag view + a PNG screenshot of the layout. This is controlled by |
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Runs a drc check on the |
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Runs spice extractions on the processed design. Based on the value of |
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Export a mag view of a given def file. |
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The input DEF file, the default is |
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The output mag file path. |
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Runs spice extractions on the processed design and performs antenna checks. The resulting file is under |
KLayout Commands¶
Most of the following commands’ implementation exists in this file
Command |
Flags |
Description |
---|---|---|
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Streams the back-up final GDSII, generates a PNG screenshot, then runs KLayout DRC deck on it. This is controlled by |
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Export a PNG view of a given GDSII or DEF file. This is controlled by |
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Output log file. |
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The input GDS or DEF file, the default is |
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Runs KLayout DRC on a |
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Runs KLayout XOR on 2 GDSIIs. This is controlled by |
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The input GDS file, the default is the magic generated GDSII under |
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The input GDS file, the default is the klayout generated GDSII under |
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The output GDS file with the xor result, the default under |
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The output XML file with the xor result, the default under |
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Opens a design in the KLayout GUI with MERGED_LEF for the cell/macro definitions. Useful as it works around KLayout’s LEF import peculiarities. |
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The input DEF file, the default is |
LVS Commands¶
Most of the following commands’ implementation exists in this file
Command |
Flags |
Description |
---|---|---|
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Runs an lvs check between an extracted spice netlist |
ERC Commands¶
Most of the following commands’ implementation exists in this [file][18]
Command |
Flags |
Description |
---|---|---|
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Runs Circuit Validity Checker Electrical Rule Checking. Voltage aware ERC checker for CDL netlists. The output files exist under |
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Deprecated: Use run_erc: Runs Circuit Validity Checker ERC on the output spice, which is a Circuit Validity Checker. Voltage aware ERC checker for CDL netlists. The output files exist under |
Utility Commands¶
Most of the following commands’ implementation exists in these files: deflef and general
Command |
Flags |
Description |
---|---|---|
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Generates a final summary csv report of the most important statistics and configurations in the run as well as a manufacturability report with the sumamry of DRC, LVS, and Antenna violations. This command is controlled by the flag |
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The ouput final summary csv report file path. |
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The ouput manufacturability report file path. |
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Removes pins from a given database. |
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The ODB file to merge the components in to. |
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The output ODB file. |
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Removes nets from a given database. |
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The ODB file to merge the components in to. |
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The output ODB file. |
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A regular expression to match to delete a certain net. Must match whole name of the net. |
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Resizes the DIEAREA in a given DEF file to the given size. |
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The input DEF file. |
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The new coordinates of the DIEARA listed as (llx, lly, urx, ury). |
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Returns the position of a given instance from the DEF view file. |
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The name of the instance. |
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The input DEF file. |
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Merges the given |
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The input LEF files. |
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Appends the components of a |
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The ODB file to merge the components in to. |
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The DEF file to merge components from. |
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The output ODB file. |
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Previously: |
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The ODB file to relocate the common pins of. |
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The DEF file to relocate pins to. |
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The output ODB file. |
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Runs a fake display buffer for the pad generator. |
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Kills the fake display buffer. |
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If |
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Attempts to execute the following command, printing the last couple of lines and either returning an error (most cases) or quitting (interactive scripts). |
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Prints |
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Prints |
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Prints |
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Prints |
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copies the GDS properties from |
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Increments |
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Adds an index prefix to the file name keeping it’s path. The prefix is |
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Finalizes the generated |
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The status message printed in the file. |
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Calls |
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Print a sorted list of *.ext files that are found in the current run directory. |
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Deprecated: use |
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The input ODB file. |
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Removed: Zeroizes the origin of all views in a LEF file. |
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The input LEF file. |